This specification relates to techniques for modifying processor performance.
Modern computer processors typically include multiple independent processor cores. Current computing systems have been optimized for efficiently handling events that take multiple milliseconds (through operating system-supported multi-programming mechanisms such as process context switches) or tens of nanoseconds (through hardware processor features such as pre-fetching, out-of-order execution, predictions, etc.).
It remains a challenge to efficiently support events that take multiple microseconds, especially when low-latency response times are required. Such microsecond-granularity events are becoming more common with high-performance networking fabrics, new non-volatile storage technologies such as Flash and phase-change-memory, or data exchanges with computing accelerators such as Graphical Processing Units (GPUs). Microsecond level events are too short to afford the overhead of context switches and operating-system interrupts, and are too long to be easily addressed by hardware processor architectural features in today's microprocessors.
Dedicating processor cores to handle specific low-latency operations, which is sometimes referred to as spinning, is a possible solution to achieving low-latency in microsecond-granularity operations. However, dedicating a processor for specific I/O operation may subtract substantial computing power from a multi-core processor.